1. Technical Field
The present invention relates to a semiconductor circuit, and more particularly, to a semiconductor integrated circuit.
2. Related Art
As shown in FIG. 1, a known semiconductor integrated circuit 1 is configured in package form by stacking a plurality of slices and coupling the plurality of stacked slices through vias, for example, through silicon vias (TSVs) so that signals may be transferred between the slices.
The lowest slice of the plurality of slices may become a master.
The TSV is a very important element that performs the transfer of a signal between the slices. Accordingly, a via test, which is a test for determining whether the TSV couples different slices electrically, must be performed.
In the known art, the via test is performed on each of the slices Slice1 and Slice2 by using a method comprising of electric current flowing in the TSV through a transistor and measuring the electric current of the master using the monitor pad 11.
The method of measuring an electric current, however, has low reliability in a test because the electric current may change due to several internal and external environmental factors.
If a circuit block 21 (for example, a circuit related to the processing of information for distinguishing slices from one another) is placed between the TSVs as in FIG. 2, the via test itself may be undesirable since an electric current may be blocked or greatly changed by the circuit block 21.